Minimal Complexity Hierarchical Loop Representations of SFG Processors for Optimal High Level Synthesis

In order to rapidly produce, using high level synthesis, quality silicon implementations of Signal Flow Graphs (SFGs) for large size, real-world signal/image processing problems, the Hardware Description Language (HDL) representations of SFG nodes should possess certain desirable characteristics. We have embedded in DG2VHDL, a design tool developed by the authors which translates automatically an algorithm's Dependence Graph into synthesizable VHDL models for SFG arrays 1], an algorithm that formulates the minimal design complexity nested loop structure (to be deened herein) for each SFG processor. This representation will, in all but some pathological cases, produce post-synthesis hardware whose area scales near optimally with increasing problem size. Furthermore , the time and memory required for the synthesis of such models does not increase with the problem size. A polynomial time heuristic is presented which nds (almost always) the minimal design complexity loop representation of SFG nodes. With the design tool DG2VHDL 1] we have automated the process of generating hardware implementations of Signal Flow Graphs (SFGs) 2]. DG2VHDL generates a fully synthesizable, hierarchical VHDL 3, 4] design that matches the cycle by cycle I/O behavior of the desired SFG array, and after synthesis gives rise to hardware that has the distributed memory and control characteristics of SFG arrays. There is a large body of literature on Dependence Graphs (DGs) and DG to SFG mappings as a method for parallelizing matrix and graph theoretic computations. DG2VHDL allows designers and researchers to quickly capture DGs and produce HDL models for various SFG architectures that are easily synthesized, tested and compared. Our group has used the tool to help create hardware implementations for a variety of problems, including image transforms (DCT 5], DWT 6]), motion estimation 7], and higher order moments estimation 8], among others. The challenge in the development of DG2VHDL was not merely the generation of VHDL but to develop an understanding of the characteristics of optimal HDL models for SFGs. We asked ourselves the following questions: If one was to derive automatically an HDL model of an SFG array, what is the best way to go about it? Is one such HDL model better than another and how does one quantify the diierence? How can we decide if we have obtained an optimal model? As the number of computations in the DG of the algorithm targeted for parallelization increase, how is the best HDL model aaected? The rest of the paper is …